SRAM device and method of manufacturing the same

ABSTRACT

A gate insulating film is formed on a main surface of a semiconductor substrate. A conductive layer P1 including a gate region G1 and a conductive layer P2 including a gate region G2 are formed on the gate insulating film. A diffusion regions D1, S, and D2 are formed with gate regions G1 and G2 interposed therebetween. The conductive layer P1 and the diffusion region D2 are put in contact with each other and the conductive layer P2 and the diffusion region D1 are put in contact with each other. On the main surface region of the substrate corresponding to the conductive layer P1, a buried diffusion layer BD1 of the same conductive type as the diffusion region S is formed contiguously to the diffusion region S. On the main surface region of the substrate corresponding to the conductive layer P2, a buried diffusion layer BD2 of the same conductive type as the diffusion region S is formed contiguously to the diffusion region S. Then, the diffusion region S is grounded.

TECHNICAL FIELD

The present invention relates to a SRAM device and a method ofmanufacturing the same.

BACKGROUND ART

In a static random access memory (SRAM) cell, one-bit is formed by aflip-flop structure. Therefore, the inverter output portion of onetransistor is put in contact with the gate of the other transistor. Theinverter output portion of the other transistor is put in contact withthe gate of the first-mentioned transistor. This is particularly called"coupling".

In manufacturing an LSI, the output portion of the inverter correspondsto the drain portion (N⁺ diffusion region) of a driver transistor(hereinafter, referred to as "pull-down transistor"). Therefore, the N⁺diffusion region must be brought into contact with the gate, to effectcoupling.

The direct contact is made as shown in FIG. 18. A polysilicon layer P1for forming a gate G1 of a transistor Q1 extends to the proximity of adrain D2 of a transistor Q2 and comes into contact with the drain D2,and a polysilicon layer P2 of the transistor Q2 extends, in a similarfashion, to the proximity of a drain D1 of the transistor Q1. As aresult, a source S serving as a ground electrode is surrounded bypolysilicon layers. Therefore, another layer must be provided for theformation of the ground wiring L. That is, an additional polysiliconlayer or an extra silicide layer (TiSi₂, WSi) is further required.

For making the coupling, the following conventional methods are known:(1) coupling is made by a second polysilicon layer and not by a firstpolysilicon layer forming the gate, and (2) coupling is made by a directcontact of the gate polysilicon of one transistor and the N+ diffusionregion of the other transistor.

In the method (1), after completion of a source/drain formation step bymeans of a CMOS process, an insulating film is removed from the gatepolysilicon of one transistor and from the N⁺ diffusion region of theother transistor, and then, a Ti silicide layer is formed thereon.Subsequently, a second polysilicon layer is formed on the resultantstructure. By way of the second polysilicon layer thus formed, the gatepolysilicon of one transistor is coupled with the N⁺ diffusion region ofthe other transistor.

However, this method has a drawback. Since three masks are required, themanufacturing process becomes complicated. Furthermore, to form contacton the gate polysilicon, the gate polysilicon must be overlapped with acontact pattern, increasing a cell size. To prevent the enlargement ofthe cell-size, a technique such as self-align contact is required. Ifso, the manufacturing steps will further increase, complicating themanufacturing process. Furthermore, this method requires to form twotypes of contacts. Therefore, the process corresponding to each of ohmiccontacts must be controlled.

In the method (2), after the gate oxide film is removed from the contactformation portion of a substrate, a gate polysilicon layer is formed.Subsequently, phosphorus glass is deposited on the gate polysiliconlayer and heat treatment is applied to the resultant structure. As aresult, phosphorus is diffused not only into the polysilicon layer butalso into the contact formation region of the substrate. In this manner,the direct contact of gate polysilicon with the N⁺ diffusion region canbe attained.

However, this method has a drawback. Since phosphorus is doped by meansof heat diffusion, the phosphorus-diffusion region becomes as large as0.5 to 1.2 μm. Hence the device thus obtained cannot be used as asubmicron device.

DISCLOSURE OF INVENTION

An object of the present invention is to provide a SRAM device capableof forming a ground wiring without providing an additional layer and toprovide a method of manufacturing the SRAM device.

Another object of the present invention is to provide a method ofcoupling the gate of one driving transistor to the diffusion region ofthe other transistor in a semiconductor device having a SRAM structurewithout preventing miniaturization and without complicating themanufacturing process.

According to a first aspect of the present invention, there is provideda SRAM device comprising: a semiconductor substrate and a plurality ofmemory cells formed on the semiconductor substrate, each of the memorycells being formed on a main surface of said semiconductor substrate andcomprising:

first, second, and third diffusion regions serving as a source region ora drain region;

a first conductive layer including a first gate region, formed on achannel region between the first diffusion region and the seconddiffusion region, with an insulating layer interposed;

a second conductive layer including a second gate region, formed on achannel region between the second diffusion region and third diffusionregion, with an insulating layer interposed;

a first contact region in which the first conductive layer is in contactwith the third diffusion region;

a second contact region in which the second conductive layer is incontact with the first diffusion region,

the first diffusion region and the third diffusion region being mutuallyopposed with the second diffusion region interposed therebetween, andthe first conductive layer and second conductive layer being positionedso as to surround the second diffusion region;

a first buried diffusion layer of the same conductive type as the seconddiffusion region formed on a main surface region of the substratecorresponding to the first conductive layer, contiguously to the seconddiffusion region; and

a second buried diffusion layer of the same conductive type as thesecond diffusion region formed on a main surface region of the substratecorresponding to the second conductive layer, contiguously to the seconddiffusion region;

wherein a first driving transistor is formed of the first diffusionregion, second diffusion region and the first conductive layer servingas a gate region; and

a second driving transistor is formed of the second conductive region,the third diffusion region and the second conductive layer;

each of memory cells includes the first and second driving transistors;

the second diffusion region is grounded; and

each of the first and second buried diffusion layers is connected to agrounded diffusion region of an adjacent memory cell, thereby forming acommon ground wiring.

According to a second aspect of the present invention, there is provideda method of manufacturing a SRAM device, comprising the steps of:

forming a gate insulating film on a main surface of a semiconductorsubstrate;

forming a first conductive layer including a first gate region on thegate insulating film;

forming a second conductive layer including a second gate region;

forming first, second, and third diffusion regions serving as a sourceor drain region, with the first gate region and the second gate regioninterposed;

bringing the first conductive layer in contact with the third diffusionregion;

bringing the second conductive layer in contact with the first diffusionregion;

forming a first buried diffusion layer of the same conductive type asthe second diffusion region on a main surface of a substratecorresponding to the first conductive layer, in a contiguous form to thesecond diffusion region;

forming a second buried diffusion layer of the same conductive type asthe second diffusion region on the main surface of a substratecorresponding to the second conductive layer, in a contiguous form tothe second diffusion region; and

grounding the second diffusion region.

According to a third aspect of the present invention, there is provideda method of coupling a conductive layer serving as a gate of one of twodriving transistors with a diffusion region of the other transistor in asemiconductor device of a SRAM structure having two driving transistorsmounted on a semiconductor substrate, the method comprises the steps of:

forming an gate insulating film on a main surface of the semiconductorsubstrate;

forming a buried diffusion layer of the same conductive type as thediffusion region to be coupled, by injecting impurities through theinsulating film into the predetermined contact formation region of amain surface of the semiconductor substrate;

forming a conductive layer serving as a gate on a portion of the gateinsulating film corresponding to the buried diffusion layer;

forming the diffusion region to overlap with the buried diffusion layer;

removing part of the insulating layer between the conductive layer andthe buried diffusion layer; and

bringing the conductive layer in contact with the buried diffusion layerby providing a conductive material around the conductive layer.

In the first and second aspects mentioned above, on the basis of theprerequisite conditions that the first conductive layer and the thirddiffusion region are in contact with each other and the secondconductive layer and the first diffusion region are in contact with eachother, a first buried diffusion layer of the same conductive type as thesecond diffusion region is formed, on the main surface of a substratecorresponding to the first conductive layer, contiguously to the seconddiffusion region. Furthermore, a second buried diffusion layer of thesame conductive type as the second diffusion region is formed on themain surface of a substrate corresponding to the second conductivelayer, contiguously to the second diffusion region. The second diffusionregion is grounded. Each of the first and second buried diffusion layersis in contact with a grounded diffusion region of an adjacent memorycell. Therefore, a common ground wiring can be formed in the diffusionregion on the main surface of a substrate. On other words, the groundwiring can be formed without providing an additional layer.

In the third aspect of the present invention, since the buried diffusionlayer is previously formed in the predetermined contact formation regionof the main surface of a semiconductor substrate by ion implantationthrough an insulating layer, the impurity diffusion region will not bebroader than required, unlike a conventional case of a direct contact.Furthermore, part of the insulating layer between the buried diffusedlayer and the conductive layer is removed and a conductive material isburied in the insulating layer removed portion, thereby putting theburied diffusion layer in contact with the conductive layer. In thisway, coupling is accomplished. Therefore, the manufacturing steps aresimplified compared to a conventional case employing a secondpolysilicon layer. Furthermore, the contact portion may be formed in asmaller size.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an equivalent circuit diagram of a SRAM device of ahigh-resistance loading type to be applied to the present invention;

FIG. 2 is an equivalent circuit diagram of a SRAM device of athin-transistor loading type to be applied to the present invention;

FIG. 3 is a schematic plan view of a SRAM device according to anembodiment of the present invention;

FIG. 4 is a view of a substrate for a SRAM device, to which a P-wellregion and an N-well region are provided;

FIGS. 5 to 17 are cross sectional views for use in explaining themanufacturing steps of a SRAM; and

FIG. 18 is a schematic plan view of a conventional SRAM device.

BEST MODE OF CARRYING OUT THE INVENTION

Hereinbelow, embodiments of the present invention will be explained.

As the SRAM device used in the present invention, either a SRAM of ahigh-resistance loading type shown in the equivalent circuit diagram ofFIG. 1 or a SRAM of a thin-film transistor (TFT) loading type may beused.

The high-resistance-loading type SRAM shown in FIG. 1 comprises fourtransistors Q₁ -Q₄ and two high-resistances R₁ and R₂. In FIG. 1, Q₁ andQ₂ are pull-down transistors. Q_(') and Q₄ are transfer-gate transistors(hereinafter, referred to as "pass- gate transistor"). WL is a wordline, BL and BL are bit lines. N₁ and N₂ are nodes, and Vcc is apositive-side power source voltage, Vss is a negative-side power sourcevoltage.

Now, we will explain how to operate the high-resistance-loading typeSRAM shown in FIG. 1.

The transistor Q2 is in the on-state and the transistor Q1 is in theoff-state. At the node S₁, if the transistor Q1 is off and thehigh-resistance-load has a sufficiently higher resistance value thanthat of the transistor, the potential can be maintained at 5 V. At thenode S₂, if the transistor Q2 is on and the high resistance load has asufficiently lower resistance value than that of the transistor, thepotential can be maintained at 0 V. However, under the aforementionedconditions, a direct current flows from the positive-side power sourcevoltage (Vcc) supply line to the negative-side power source voltage(Vss) supply line, by way of the node S₂. The value of the directcurrent is inversely proportional to the value of the high resistanceload R₂.

The SRAM of a TFT loading type shown in FIG. 2 comprises fourtransistors Q₁ to Q₄, similarly to FIG. 1, and two TFT loadinghigh-resistances Q₅ and Q₆. In FIG. 2, WL represents a word line. BL andBL are bit lines. N1 and N2 are nodes. Vcc is a positive-side powersource voltage. Vss is a negative-side power source voltage.

Now, we will explain how to operate the TFT-loading-type SRAM. If thepositive-side power source voltage Vcc is set to 5 V and the negativepower source voltage Vss is set to 0 V, the node N1 becomes 5 V and thenode N2 becomes 0 V. In this case, the transistor Q2 is on andtransistor Q6 is off, at the same time, the transistor Q1 is off andtransistor Q5 is on. At the node N₁, if the transistor Q1 is off and aresistance value of the transistor Q1 is sufficiently higher than thatof the on-state transistor Q5, the potential can be maintained at 5 V.At the node N₂, if the transistor Q2 is on and the resistance valuethereof is sufficiently lower than that of the off-state transistor Q6,the potential can be maintained at 0 V.

Hereinbelow, we will explain a gist portion of the SRAM device accordingto an embodiment of the present invention. FIG. 3 is a schematicplan-view showing the gist portion. The SRAM device comprises a firstpull-down transistor Q1 , a second pull-down transistor Q2, a firstpass-gate transistor Q3, and a second pass-gate transistor Q4. The SRAMdevice further comprises first and second load elements (not shown)constituted of a high-resistance-loading transistor or a TFT transistor.One memory cell is constructed of these six elements. (cell A shown inFIG. 3 is explained herein).

In the memory cell, a source S1 and a drain D1 of a first pull-downtransistor Q1, and a source S2 and a drain D2 of a second pull-downtransistor Q2 are formed as diffusion regions on the main surface of thesubstrate. Note that the sources S1 and S2 are formed in common,constituting a source S.

On the main surface of the substrate, a polysilicon layer P1 for forminga gate G1 of the transistor Q1 and a polysilicon layer P2 for forming agate G2 of the transistor Q2 are formed. The polysilicon layer P1extends to the proximity of the drain (diffusion region) D2 of thetransistor Q2 and comes into direct contact with the main surface of thesubstrate at a direct contact portion DC2. The direct contact portionDC2 is connected to drain D2. As a result, the gate G1 of the transistorQ1 is coupled with the drain D2 of the transistor Q2.

Note that the polysilicon layers P1 and P2 are simultaneously formed ina single step.

Buried diffusion layers BD1 and BD2 of the same conductive type as thesource region are formed adjacent to the source regions S1 and S2grounded and positioned immediately under the polysilicon layers P1 andP2. With this structure, the source region can be formed contiguously toburied diffusion layers BD1 and BD2.

Adjacent to a memory cell A explained herein, a cell B and a cell Chaving the same structure are formed. If these buried diffusion layersBD1 and BD2 are formed contiguously to the source regions of the cell Band the cell C, respectively, the resultant structure can be used as acommon ground wiring. Hence, an additional layer is not required forgrounding.

In the figure, WL1 is an upper word line and WL2 is a lower word line.Both are formed of the same layer as the polysilicon layers P1 and P2.

Hereinbelow, we will explain the steps of manufacturing the SRAM devicehaving the aforementioned structure with reference to FIGS. 4 to 17.Note that a resistance load element is also omitted from the figures.

According to a commonly-used method, at first, a P-well region 2 and anN-well region 3 are formed in an N-type substrate 1 as shown in FIG. 4.Then, to separate these elements, a field oxide film 4 and a p-typeregion 5 are formed.

In the following steps, only a memory portion will be explained which isdirectly related to the present invention. Note that FIGS. 5 to 17 arecross sectional views taken along the line A-A' of FIG. 3.

As shown in FIG. 5, a pregate oxide film 6 is formed on the main surfaceof the P-well region 2, by thermal oxidation. Subsequently, p-typeimpurities such as boron are doped, effecting channel doping. Then, aresist 7 serving as a photo-mask is formed on the region excluding thedirect contact formation regions DC and BD explained in FIG. 3.Thereafter, N-type impurities such as As are doped into the regions DCand BD through the gate oxide film 6. In this case, the acceleratingvoltage is set to 100 KeV, and the dosage is set to 4×10¹⁵.

By doping the N-type impurities, N-type buried diffusion layers 8 and 9are formed under the oxide film in the regions DC and BD.

The depths of the buried diffusion layers 8 and 9 are as sufficientlysmall as at most 0.2 μm. The buried diffusion layer 8 is used for theaforementioned direct contact (the details will be described later). Theburied diffusion layer 9 is used for the formation of the ground wiring,as mentioned above.

Thereafter, the pregate oxide film 6 is subjected to gate oxidation toprovide a gate oxide film 6', as shown in FIG. 6, and then, apolysilicon film 10 is deposited on the gate oxide film 6'. On thepolysilicon layer 10, a phosphorus glass layer is formed and treatedwith heat treatment. In this manner, phosphorus is diffused in thepolysilicon layer 10. After the phosphorus glass is removed, thepolysilicon layer 10 is subjected to post oxidation. As a result, a SiO₂layer 11 is formed on the polysilicon layer 10.

Then, as shown in FIG. 7, a resist film 12 serving as a photo-maskhaving a predetermined pattern is formed on a SiO₂ layer 11. The SiO₂layer 11 and the polysilicon layer 10 are etched. As a result, thepolysilicon layer 10 including the gate is patterned in thepredetermined form.

Furthermore, as shown in FIG. 8, to the portion of the resultantstructure on which the polysilicon layer 10 is not formed, N-typeimpurities are doped at a low concentration to form a shallow N⁻ LDDregion 13.

Subsequently, a side wall SiO₂ 14 is formed as shown in FIG. 9 and theetching-back of the oxide film is effected. Thereafter, N-typeimpurities such as As are doped at a high concentration to form asource/drain. In this manner, the N⁺ region 15 is formed relativelydeeper, providing, source/drain regions 16 and 17 having an LDDstructure.

Thereafter, as shown in FIG. 10, the oxide layer of the polysiliconlayer 10 in the direct contact region DC is removed by etching, using aresist 18 as a mask. In the region DC, as shown in the enlarged view ofFIG. 11, a SiO₂ layer 11 formed on the polysilicon layer 10 and the sidewall SiO₂ 14 are completely removed. The gate oxide film 6' immediatelyunder the polysilicon layer 10 is removed from the both ends of thepolysilicon layer 10 by 0.1 μm or more in length.

As shown in FIG. 12, titanium is deposited on the region DC and heat isapplied thereto, thereby forming a titanium silicide (TiSi₂) region 19.Thereafter, titanium attached on the outside is removed. W may bedeposited in place of Ti to form WSi.

The structure of this step is shown in the enlarged view of FIG. 13. Asshown in FIG. 13, the TiSi₂ region 19 is also formed between thepolysilicon layer 10 and the buried diffusion layer 8. By the presenceof the TiSi₂ region thus formed, the polysilicon layer 10 can be broughtinto direct contact with the buried diffusion layer 8 without otherpolysilicon layer interposed therebetween.

An interlayer insulating film 20 is formed as shown in FIG. 14. Theinterlayer insulating film 20 is formed by depositing, for example, NSGand then BPSG, followed by subjecting to densify treatment.

As a next step, a desired contact hole (not shown) is formed by contactetch, and tungsten is deposited in the contact hole thus formed, therebyaccomplishing etching back.

Thereafter, as shown in FIG. 15, a barrier metal layer 21 are depositedon the interlayer insulating layer 20. On the resultant structure, afirst metal layer 22 (for example, formed of aluminium) serving as alower word line is deposited. Afterwards, unnecessary portions areremoved by etching.

Over the entire surface of the resultant structure, an oxide film isformed. The oxide film is not particularly limited. As the oxide film,used herein is an intermetal oxide layer 26 formed of two oxide films 23and 24 with a metal layer 25 such as SOG interposed therebetween, asshown in FIG. 16.

Thereafter, as shown in FIG. 17, the oxide films 23 and 24 are etched toform a via hole 27 reaching the first metal layer 22. In the via hole 27and on the oxide film 24, a second metal layer 28 (for example, formedof aluminium) serving as an upper word line is formed. Note that thefirst metal layer 22 is communicated with the second metal layer 28 byway of the via hole 27.

Afterwards, an oxide film and a nitride film are formed on the resultantstructure, as needed, and then subjected to desired treatment. In thisway, the SRAM device is accomplished.

In the SRAM device having such a structure, the buried diffusion layer 9of the same conductive type as the diffusion region (source) 16 isformed on the main surface portion of the substrate corresponding to theconductive layer 10, contiguously to the diffusion region 16. The burieddiffusion layer 9 is further connected contiguously to the diffusionregions of the memory cells adjacent thereto. As a result, a commonground wiring can be formed on the main surface of the substrate.Therefore, a ground wiring is formed without providing an additionallayer.

To bring the drain region 17 into contact with the polysilicon layer 10extended from a gate of another transistor in the manufacturing processof the SRAM, the buried diffusion layer 8 is previously formed by ionimplantation on the predetermined contact formation region with theinsulating layer interposed. As a result, an impurity-diffusion regionwill not be broader than required, unlike a conventional direct-contactformation case. Therefore, a fine pattern can be sufficiently formed inthis case. Furthermore, the polysilicon layer 10 is brought into directcontact with the buried diffusion layer 8 without a second polysiliconlayer interposed by providing TiSi₂ around the polysilicon layer 10 inthe predetermined contact formation region DC. Hence, the manufacturingsteps are simplified and the contact portion may be smaller, compared tothe case of employing a second polysilicon layer.

The buried diffusion layer 8 is overlapped with the drain 17, with theresult that the polysilicon layer 10 becomes in couple with the drain 17by way of the buried diffusion layer 8.

In the explanation above, polysilicon was used as the conductive layer.However, the conductive layer is not limited to polysilicon, and othermaterials such as a silicide and an amorphous silicon may be used.Furthermore, TiSi₂ or Wsi was employed as the conductive material to beprovided around the conductive layer. However, the conductive materialis not limited to them. Other conductive materials may be used.Furthermore, the SRAM device is not limited to an N-channelsemiconductor. A P-channel semiconductor is also applicable.

I claim:
 1. A SRAM device comprising a semiconductor substrate and aplurality of memory cells formed on said semiconductor substrate, eachof said memory cells being formed on a main surface of saidsemiconductor substrate and comprising:first, second, and thirddiffusion regions serving as a source region or a drain region; a firstconductive layer including a first gate region, formed on a channelregion between the first diffusion region and the second diffusionregion, with an insulating layer interposed; a second conductive layerincluding a second gate region, formed on a channel region between thesecond diffusion region and third diffusion region, with an insulatinglayer interposed; a first contact region in which said first conductivelayer is in contact with said third diffusion region; a second contactregion in which said second conductive layer is in contact with saidfirst diffusion region; said first diffusion region and said thirddiffusion region being mutually opposed with said second diffusionregion interposed therebetween, and said first conductive layer andsecond conductive layer being positioned so as to surround said seconddiffusion region; a first buried diffusion layer of the same conductivetype as the second diffusion region formed on a main surface region ofthe substrate corresponding to said first conductive layer, contiguouslyto said second diffusion region; and A second buried diffusion layer ofthe same conductive type as the second diffusion region formed on a mainsurface region of the substrate corresponding to said second conductivelayer, contiguously to said second diffusion region, wherein a firstdriving transistor is formed of said first diffusion region, seconddiffusion region and said first conductive layer serving as a gateregion; and a second driving transistor is formed of said secondconductive region, said third diffusion region and said secondconductive layer; said each of memory cells includes said first andsecond driving transistors; said second diffusion region is grounded;and each of said first and second buried diffusion layers is connectedto a grounded diffusion region of an adjacent memory cell, therebyforming a common ground wiring.
 2. A method of manufacturing a SRAMdevice, comprising the steps of:forming a gate insulating film on a mainsurface of a semiconductor substrate; forming a first conductive layerincluding a first gate region on said gate insulating film; forming asecond conductive layer including a second gate region; forming first,second, and third diffusion regions serving as a source or drain region,with said first gate region and said second gate region interposed;bringing said first conductive layer in contact with said thirddiffusion region; bringing said second conductive layer in contact withsaid first diffusion region; forming a first buried diffusion layer ofthe same conductive type as the second diffusion region on a mainsurface of a substrate corresponding to said first conductive layer, ina contiguous form to said second diffusion region; forming a secondburied diffusion layer of the same conductive type as the seconddiffusion region on a main surface of a substrate corresponding to saidsecond conductive layer, in a contiguous form to said second diffusionregion; and grounding said second diffusion region.
 3. A method ofcoupling a conductive layer serving as a gate of one of two drivingtransistors with a diffusion region of the other transistor in asemiconductor device of a SRAM structure having two driving transistorsmounted on a semiconductor substrate, the method comprises the stepsof:forming an gate insulating film on a main surface of saidsemiconductor substrate; forming a buried diffusion layer of the sameconductive type as said diffusion region to be coupled, by injectingimpurities through said gate insulating film into the predeterminedcontact formation region of a main surface of said semiconductorsubstrate; forming a conductive layer serving as a gate on a portion ofsaid gate insulating film including a portion corresponding to saidburied diffusion layer; forming said diffusion region to overlap withsaid buried diffusion layer; removing part of said insulating filmbetween said conductive layer and said buried diffusion layer; andbringing said conductive layer in contact with said buried diffusionlayer by providing a conductive material around said conductive layer.